发明名称 A low-jitter end-to-end latency control scheme for isochronous communications based on transmitter timestamp information
摘要 <p>A latency control mechanism for a communication system provides a known constant end-to-end delay between an audio source and one or more end node destinations, even in the case where different paths are used to reach the end nodes. A very low jitter time on the end-to-end latency is obtained, and the latency is controllable within a given range in dependence on the constraints imposed by the implementation. A block RX DPLL and latency control unit 315 adjusts the reading moment and position from the RX buffer 305 so that a delay between the time stamp taken at the source side 200 by the transmitter time stamp unit 210, and the time stamp taken at the receiver side 300 by receiver time stamp unit 310 is constant and equal to a given value.</p>
申请公布号 EP2341744(A2) 申请公布日期 2011.07.06
申请号 EP20100196165 申请日期 2010.12.21
申请人 NXP B.V. 发明人 PHILIPS, NORBERT;JANSSENS, MARK;THOEN, STEVEN
分类号 H04W56/00;H04J3/06 主分类号 H04W56/00
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