发明名称 DELAY LOCKED LOOP
摘要 PURPOSE: A delay locked loop is provided to improve noise property by making a time required for locking loop different. CONSTITUTION: A replica delay oscillator(210) generates a replica oscillation signal. A clock control part(220) receives a clock signal. A divider(230) divides the replica oscillation signal and clock signal by a first dividing ratio or a second dividing ratio. A pulse generator(240) generates a delay pulse. The delay pulse has a pulse width corresponding to a delay required for locking loop. A code value output unit(250) adjusts a code value corresponding to the pulse width of the delay pulse. A delay line(260) delays the clock signal.
申请公布号 KR20110076298(A) 申请公布日期 2011.07.06
申请号 KR20090132975 申请日期 2009.12.29
申请人 HYNIX SEMICONDUCTOR INC. 发明人 AHN, SEUNG JOON;LEE, JONG CHERN
分类号 G11C11/407;G11C8/00;G11C11/4076 主分类号 G11C11/407
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