| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an approach compatible with degradation in performances for phase noises and jitter in an output clock characteristics, which are problems in a conventional digital PLL. <P>SOLUTION: In some embodiments, a digital PLL is disclosed having a dynamically controllable filter for changing effective DPLL band width in response to one or more real time performance parameters for example a phase error etc. When a high band width is not needed, it may be controlled so as to be a comparatively low level, thereby jitter of the output clock is reduced. Alternatively, when the high band width is needed, for example, when the phase error is high in a loop, the filter can be controlled so as to improve response of the loop and to provide a comparatively high loop band width for tracking a standard clock. <P>COPYRIGHT: (C)2011,JPO&INPIT |
