发明名称 |
Methods For Generating Representations of Flatness Defects on Wafers |
摘要 |
Methods are disclosed for generating a representation of flatness defects on a wafer. Data is received describing the thickness of the wafer at a plurality of points on a wafer divided into a plurality of sites. A reference plane is defined for each of the plurality of sites. For each of the sites, an upper plane and a lower plane are defined relative to the reference plane. A determination is made as to which of the plurality of points on the wafer represents a flatness defect by identifying which points are not disposed between the upper plane and lower plane. A representation is then generated depicting a location of each of the flatness defects on the wafer. In some embodiments, a single representation is generated depicting the location of flatness defects on a plurality of wafers.
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申请公布号 |
US2011160890(A1) |
申请公布日期 |
2011.06.30 |
申请号 |
US20090648613 |
申请日期 |
2009.12.29 |
申请人 |
MEMC ELECTRONIC MATERIALS, INC. |
发明人 |
PITNEY JOHN A. |
分类号 |
G06F19/00;G01B21/30;G06F17/00 |
主分类号 |
G06F19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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