| 摘要 |
A test apparatus and a test method with which a circuit size can be decreased are provided. A recovered clock generating circuit generates a recovered clock of which phase is approximately the same as a phase of output data output by a device under test (DUT). The recovered clock generating circuit includes a phase comparator that compares a phase of the output data of the DUT to a phase of the recovered clock to generate a phase difference signal, a binary counter of which output value is incremented or decremented based on the phase difference signal, a control signal generating section that generates a control signal based on an output value of the binary counter, and a phase shifter that shifts the phase of the reference clock based on the control signal.
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