| 摘要 |
A block decoder of a semiconductor memory device includes a control signal generation circuit configured to generate an initial control signal and a block selection control signal in response to memory block selection addresses, an output node control circuit configured to set up an initial voltage of an output node in response to the initial control signal, and a block selection signal generation circuit configured to generate a block selection signal by raising a potential of the output node in response to the block selection control signal and the initial voltage of the output node.
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