| 摘要 |
<p>A semiconductor memory chip comprises a sense amplifier that amplifies data that is read from a real memory cell in response to activation by a sense amplifier enable signal; a replica circuit, further comprising a plurality of replica units connected serially, each replica unit further comprising a plurality of dummy memory cells connected in parallel, wherein the dummy memory cells of the corresponding replica unit are made read accessible in response to the data that is read from the dummy memory cells of the preceding replica unit; and an operation control circuit that activates the dummy access signal for read-accessing the dummy memory cells of the first replica unit in response to the read command, and activates the sense amplifier enable signal in response to the data that is read from the last replica unit. It is thus possible to equalize the transistor-characteristic variation in the dummy memory cells, and to optimize the sense amplifier activation timing.</p> |
