<p>A multithreaded processor with a multithreaded instruction cache and means for accessing a register file associated with the instruction cache via a thread identifier for the thread. The register file includes a data operand and an address operand, and the register file includes a plurality of thread identifiers for a plurality of threads.</p>
申请公布号
EP2339457(A2)
申请公布日期
2011.06.29
申请号
EP20110001890
申请日期
2005.04.07
申请人
ASPEN ACQUISITION CORPORATION
发明人
HOKENEK, ERDEM;MOUDGILL, MAYAN;SCHULTE, MICHAEL J.;GLOSSNER, C. JOHN