发明名称 PHASE LOCKED LOOP AND METHOD FOR DRIVING THE SAME
摘要 PURPOSE: A phase locked loop and a method for driving the same are provided to remove the phase offset between a reference clock and a feedback clock by implementing a phase locked loop and a delay locked loop. CONSTITUTION: In a phase locked loop and a method for driving the same, a phase locked loop(100) compares the phase of a feedback clock with the phase of a reference clock. The phase locked loop generates an internal clock. A delay locked loop(200) compares the internal clock with the reference clock. The delay locked loop generates a feedback clock. The feedback clock is delayed according to a control voltage. An initial voltage driving unit(300) applies an initial voltage to a control voltage.
申请公布号 KR101045072(B1) 申请公布日期 2011.06.29
申请号 KR20090131949 申请日期 2009.12.28
申请人 HYNIX SEMICONDUCTOR INC. 发明人 KIM, KWAN DONG
分类号 G11C8/00;G11C11/407;H03L7/08 主分类号 G11C8/00
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