发明名称 Circuit to reduce duty cycle distortion
摘要 A method and a circuit for correcting duty cycle distortion. A delay insertion gate corrects data dependent delay distortion that is generated by CMOS flip-flop circuits. The delay insertion gate includes two field effect transistors and a current mirror. The two transistors each respectively receive an input signal from an upstream circuit. At least one of the transistors is coupled to an output node. The output node temporarily holds a voltage state within the delay insertion gate, correcting any distortion in the duty cycle of the input signals.
申请公布号 US7969224(B2) 申请公布日期 2011.06.28
申请号 US20090486579 申请日期 2009.06.17
申请人 HONEYWELL INTERNATIONAL, INC. 发明人 WERKING PAUL M.
分类号 H03K17/62 主分类号 H03K17/62
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