发明名称 Digital correction of nonlinearity errors of multibit delta-sigma digital to analog converters
摘要 Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.
申请公布号 US7969335(B2) 申请公布日期 2011.06.28
申请号 US20080041204 申请日期 2008.03.03
申请人 AGERE SYSTEMS INC. 发明人 ARIAS JESUS;KISS PETER;RANSIJN JOHANNES G.;YODER JAMES D.
分类号 H03M1/10 主分类号 H03M1/10
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