发明名称 |
Method, system, and program product for automated verification of gating logic using formal verification |
摘要 |
Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will be stable or unstable under a gating condition. If the test shows a design is unstable under the gating condition; it is indicated that a hardware design fix for the device design is required. If not, the test ends.
|
申请公布号 |
US7971166(B2) |
申请公布日期 |
2011.06.28 |
申请号 |
US20080139483 |
申请日期 |
2008.06.15 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
SEIGLER ADRIAN E.;VAN HUBEN GARY A. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|