| 摘要 |
Methods, circuits, processes, devices, and/or arrangements for a non-volatile memory (NVM) cell operable at relatively low voltages are disclosed. In one embodiment, an NVM cell can include: (i) a gate over a charge trapping layer, the charge trapping layer being insulated from the gate by a first insulating layer, the charge trapping layer being insulated from a channel by a second insulating layer; and (ii) source and drain on either side of the channel, the channel being under the second insulating layer, where the NVM cell is configured to be erased by channel-induced hot holes (CHH).
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