A COUNTER ARCHITECTURE FOR ONLINE DVFS PROFITABILITY ESTIMATION

摘要

A counter architecture and a corresponding method are provided for estimating a profitability value of DVFS for a unit of work running on a computing device. The counter architecture and the corresponding method are arranged for dividing total execution time for executing a unit of work on the computing device into a pipelined fraction subject to clock frequency and a non-pipelined fraction due to off-chip memory accesses, and for estimating the DVFS profitability value from the pipelined and the non-pipelined fraction.