In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.
申请公布号
WO2011075246(A2)
申请公布日期
2011.06.23
申请号
WO2010US56320
申请日期
2010.11.11
申请人
INTEL CORPORATION;DIXON, MARTIN G.;RODGERS, SCOTT D.;GUNTHER, STEPHEN H.;SETHI, PRASHANT;BAHRAMI, TARANEH;HAMMARLUND, PER
发明人
DIXON, MARTIN G.;RODGERS, SCOTT D.;GUNTHER, STEPHEN H.;SETHI, PRASHANT;BAHRAMI, TARANEH;HAMMARLUND, PER