| 摘要 |
<P>PROBLEM TO BE SOLVED: To stabilize a clock phase synchronization circuit over a long period and to reduce input disturbance influence, in relation to a clock phase synchronization circuit for outputting a clock having a phase synchronized with that of a reference clock. <P>SOLUTION: This clock phase synchronization circuit for obtaining an output signal d of a voltage-controlled oscillator 1 synchronized with the phase of reference input (a) includes: a storage means such as a memory inputting phase difference detection signals b obtained by making the frequency of the reference input (a) coincide with that of the output signal d of the voltage-controlled oscillator 1 and by comparing the phases thereof on a predetermined timing basis by a phase comparator 3 and sequentially storing them for a predetermined period; and an arithmetic processing means to obtain differences of the phase difference detection signals on a predetermined period basis as a phase variation, converting the phase variation to a control voltage of the voltage-controlled oscillator 1 corresponding to the phase variation when the phase variation is within an allowable range, and inputting a control voltage c into the voltage-controlled oscillator 1 as a control voltage corresponding to the previous phase variation or a control voltage for bringing the voltage-controlled oscillator into a free-running state when the phase variation is not within the allowable range. <P>COPYRIGHT: (C)2011,JPO&INPIT |
