| 摘要 |
PURPOSE: An adaptive digital phase locked loop is provided to change valid DPLL bandwidth in response to more than one real time performance parameters, by using a dynamically controllable filter. CONSTITUTION: A DPLL(100) provides a stable output clock by locking a phase and a frequency of a feedback clock. A DCO(140) provides individual sets of output frequencies. A 1/N divider(150) generates a one feedback clock cycle per every N clock cycle from the DCO. A PFD(110) generates a quantized output proportional to the phase error. The output of PFD induces correction of the frequency of the DCO through a digital filter(120).
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