发明名称 CELL LIBRARY, LAYOUT METHOD, AND LAYOUT APPARATUS
摘要 <p><P>PROBLEM TO BE SOLVED: To prepare a layout drawing, which does not cause a defect easily, through simple processing. <P>SOLUTION: In a cell library that is used for layout design of a semiconductor integrated circuit and is a library of design data of cells each achieving a unit function; each of the design data comprises an attribute value indicating whether the cell easily causes a defect in a cell adjacently placed across the edge and whether a defect is easily caused by a cell adjacently placed across the edge, and attribute information that is associated with the attribute value. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP2011124423(A) 申请公布日期 2011.06.23
申请号 JP20090281574 申请日期 2009.12.11
申请人 TOSHIBA CORP 发明人 SANO FUMIHIKO
分类号 H01L21/82;G03F1/68;G03F1/70;G06F17/50;H01L21/027 主分类号 H01L21/82
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