发明名称 CODER
摘要 A coder has a binarizing circuit (130) for converting multivalued data into a binary symbol sequence, the multivalued data being generated from an input signal and having a plurality of contexts, an arithmetic code amount approximating circuit (200) for calculating a prediction code amount in the predetermined coding unit from the binary symbol sequence, and a coding circuit (102) for coding the input signal arithmetically on the basis of the prediction code amount. The arithmetic code amount approximating circuit (200) includes a selector (230) for dividing the binary symbol sequence into a plurality of groups based on the contexts, a plurality of code amount approximating circuits (211-214) for calculating, from the binary symbol sequence divided into a plurality of groups, the prediction code amount of the group based on at least the section range in arithmetic coding, and an adder (231) for adding the prediction code amounts from all code amount approximating circuits and outputting the prediction code amount in the specified coding unit.
申请公布号 EP2091257(A4) 申请公布日期 2011.06.22
申请号 EP20070829562 申请日期 2007.10.11
申请人 PANASONIC CORPORATION 发明人 TANAKA, TOSHIHIRO;ISHIDA, KEIICHI
分类号 H03M7/40;H04N1/41;H04N19/00;H04N19/13;H04N19/134;H04N19/136;H04N19/146;H04N19/189;H04N19/423;H04N19/593;H04N19/60;H04N19/61;H04N19/625;H04N19/85;H04N19/91 主分类号 H03M7/40
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