发明名称 WAFER LEVEL CHIP SCALE PACKAGE AND ITS FABRICATION METHOD
摘要 PURPOSE: A wafer level chip scale package and its fabrication method are provided to prevent the deterioration of a device by installing a refrigerant layer inside a passivation layer in a region excluding a device reserved area. CONSTITUTION: A first passivation layer(216) is formed in upper part of a structure in which the semiconductor device is formed. A refrigerant layer(218) is formed inside the first passivation layer. A refrigerant is inserted in a region excluding a device reserved area. A second passivation layer(220) is formed on the first passivation layer including the refrigerant layer. A refrigerant layer receives the refrigerant by forming the first passivation layer in a refrigerant input hole through a dry etching process. The first passivation layer and the second passivation layer are formed by using glass.
申请公布号 KR20110068489(A) 申请公布日期 2011.06.22
申请号 KR20090125468 申请日期 2009.12.16
申请人 DONGBU HITEK CO., LTD. 发明人 JUNG, OH JIN
分类号 H01L23/42 主分类号 H01L23/42
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