发明名称 DATA DERATE MATCHER AND METHOD THEREOF
摘要 PURPOSE: A data derate matcher and method thereof are provided to form a sub block deinterleaver of a derate matcher by a deinterleaving method, thereby reducing signal processing time. CONSTITUTION: A bit separating unit(302) divides each bit data of an input bit string into three kinds of bit strings. Address generators(316,318,320) generate an address of available data to be used during a process of deinterleaving data of each bit string separated from the bit separating unit. Sub block deinterleavers(310,312,314) successively receive data of an address designated by the address generators. The sub block deinterleavers output deinterleaved output bit string data.
申请公布号 KR20110068104(A) 申请公布日期 2011.06.22
申请号 KR20090124942 申请日期 2009.12.15
申请人 ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE 发明人 KIM, NAM IL;KIM, DAE HO
分类号 H03M13/27;H03M13/23;H04B1/06 主分类号 H03M13/27
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