METHOD OF FPGA TECHNOLOGY MAPPING BASED ON LUT FOR MINIMIZATION OF DELAY TIME

摘要

PURPOSE: A method of FPGA technology mapping based on LUT for minimization of delay time is provided to improve the performance of the entire system by producing a cost function in which design area and time-delay are considered and a division cost function in which a dynamic programming method is applied. CONSTITUTION: A combinational logic circuit for the look-up table mapping(LUT mapping) is extracted from the input order circuit(S100). The arrival time of the input signal for the gate input and output of the combination logic circuit is calculated(S200). The combination logic circuit is converted to a DAG graph type(S300). A tree is divided based on the nodes which have two or more fan-out in the DAG graph(S400). The LUT circuit of the combination logic circuit is created by mapping the trees divided into dynamic program schemes(S500). A LUT net list is created by assigning the state memory elements to each of the flipflop of the LUT circuit(S600).