发明名称 |
Replacing cache lines in a cache memory |
摘要 |
In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the data. In various implementations, the weight can be based on the cache coherency state and a recency of usage of the data. Other embodiments are described and claimed. |
申请公布号 |
EP2336892(A1) |
申请公布日期 |
2011.06.22 |
申请号 |
EP20100195242 |
申请日期 |
2010.12.15 |
申请人 |
INTEL CORPORATION |
发明人 |
KUMAR, AKHILESH;CHERUKURI, NAVEEN;BRZEZINSKI, DENNIS W.;SCHOINAS, IOANNIS T;SHAYESTEH, ANAHITA;AZIMI, MANI |
分类号 |
G06F12/12;G06F12/08 |
主分类号 |
G06F12/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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