| 摘要 |
Techniques are disclosed for improving the dynamic performance of digital-to-analog converters (DAC), by compensating for the unique delay characteristics of each bit in the DAC summing junction to equalize the delays. In one example case, a DAC device is provided that includes a plurality of current sources and a plurality of switches, each switch operatively coupled between a corresponding one of the current sources and a summing junction that is operatively coupled to an analog output. The device further includes a plurality of switch control lines configured to receive a digital input, each switch control line for controlling a corresponding one of the switches. The device further includes a plurality of compensation delay elements, each associated with a corresponding one of the switch control lines and providing a different delay value.
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