发明名称 CIRCUIT OF BUS SIGNALS CONTROL AND CIRCUIT OF SIGNALS PROCESSING WITH CIRCUIT OF BUS SIGNALS CONTROL
摘要 FIELD: information technologies. ^ SUBSTANCE: unit of memory control, recording and reading data of a slave device according to a command from a master device. A bus diagnostics line is directly connected from the bus signal control circuit with a receiving terminal of the slave device bus signals without passage through an address bus and a control signal line. A unit of bus signals abnormality processing compares the output signal of the bus coming out of the bus signal control circuit into the address bus and the control signal line with a signal of the bus feedback supported with the feedback via the bus diagnostics line, in order to detect availability/unavailability of the difference. The memory control unit extends a period of the performed bus cycle operation, when it is defined in the unit of the bus signals abnormality processing that the difference is available. ^ EFFECT: provision of a circuit for bus signals control, which may reliably detect errors in addressing. ^ 8 cl, 12 dwg
申请公布号 RU2421782(C2) 申请公布日期 2011.06.20
申请号 RU20090118689 申请日期 2009.05.18
申请人 KABUSIKI KAJSJA TOSIBA 发明人 TAKEKHARA DZJUN;ARAMAKI NARUKHIKO;KAVAMURA TOSIKADZU;SAMEDA JOSITO;NAKATANI KHIROSI;OKABEH MOTOKHIKO;JOSIDA JUKITAKA
分类号 G06F9/00 主分类号 G06F9/00
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