发明名称 RECEIVING CIRCUIT
摘要 <p>A receiving circuit includes a frame memory to store received data of one frame, a de-rate matching circuit to generate data before encoding by reading the received data from the frame memory and performing de-rate matching in a reverse manner to rate matching performed on the received data at a transmitting end, and a TTI memory to store the data before encoding.</p>
申请公布号 KR101042876(B1) 申请公布日期 2011.06.20
申请号 KR20080118387 申请日期 2008.11.26
申请人 发明人
分类号 H04B1/16;H04L1/00;H03M13/27;H04J13/00 主分类号 H04B1/16
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