PHASE LOCKED LOOP WITH DIGITAL COMPENSATION FOR ANALOG INTEGRATION
摘要
<p>A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal, The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage controlled oscillator (VCO).</p>
申请公布号
WO2011071953(A1)
申请公布日期
2011.06.16
申请号
WO2010US59337
申请日期
2010.12.07
申请人
QUALCOMM INCORPORATED;DUNWORTH, JEREMY D.;BALLANTYNE, GARY J.;ASURI, BHUSHAN S.;GENG, JIFENG;SAHOTA, GURKANWAL S.
发明人
DUNWORTH, JEREMY D.;BALLANTYNE, GARY J.;ASURI, BHUSHAN S.;GENG, JIFENG;SAHOTA, GURKANWAL S.