发明名称 |
Digital Pulse Width Modulator |
摘要 |
A DPWM (1) has a locked loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each cell in the loop (35). A multiplexer (5) selects one of the cell outputs at any one time. This allows the DPWM (1) to have a greater resolution which would otherwise be achieved with the same input clock. The resolution is further increased using an interpolator. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output.
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申请公布号 |
US2011141780(A1) |
申请公布日期 |
2011.06.16 |
申请号 |
US20100961975 |
申请日期 |
2010.12.07 |
申请人 |
O'MALLEY EAMON;RINNE KARL |
发明人 |
O'MALLEY EAMON;RINNE KARL |
分类号 |
H02M7/00 |
主分类号 |
H02M7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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