发明名称 DETERMINATION DEVICE AND DETERMINATION METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a determination device for specifying the failure place of a semiconductor integrated circuit equipped with a plurality of data processing circuits. <P>SOLUTION: A determination device related with one embodiment of this invention is configured to determine whether or not an LSI20A equipped with a first OSD plane 23A, a second OSD plane 23B and a video plane 23C is good. A region A corresponding to the output from the first OSD plane 23A and a region B corresponding to the output from the second OSD plane 23B are set as a region for performing a CRC arithmetic operation in an image of one frame formed by a plurality of image processing circuits according to an input test pattern. A CRC arithmetic circuit 15 performs the CRC arithmetic operation of the region A and the region B to calculate each arithmetic result, and compares an expectation value corresponding to each region with the arithmetic result, and outputs the result of comparison to a CPU 22 which determines whether or not the plurality of data processing circuits are good. <P>COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011118571(A) 申请公布日期 2011.06.16
申请号 JP20090274250 申请日期 2009.12.02
申请人 RENESAS ELECTRONICS CORP 发明人 NOGAMI NAOKEN
分类号 G06F11/22;G06F11/10;G09G5/00 主分类号 G06F11/22
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