发明名称 MEMORY DEVICE AND METHOD
摘要 A device is disclosed having a memory module (16) that comprises a first memory block (22), a second memory block (23), a programmable storage location, and a memory controller (26). The first memory block (22) of non-volatile memory comprises a plurality of word locations and an address decoder (201) coupled to a first access port of the memory controller (26). The address decoder (201) to select one of the plurality of word locations for access in response to receiving address information via the first access port. The second memory block (23) comprising a plurality of word locations and an address decoder (201) coupled to a second access port of the memory controller (26). The address decoder (201) to select one of the plurality of word locations for access in response to receiving address information via the second access port. The memory controller (26) comprising an input coupled to the programmable storage location (25), and to access, in response to the programmable configuration information having a first value, a first portion of the first memory block (22) and a first portion of the second memory block (23) as interleaved memory, a second portion of the first memory block (22) as non-interleaved memory, and a second portion of the second memory block (23) as non-interleaved memory.
申请公布号 WO2011034673(A3) 申请公布日期 2011.06.16
申请号 WO2010US45573 申请日期 2010.08.16
申请人 FREESCALE SEMICONDUCTOR INC.;BORRACINI, EVANDRO JOSE PITARO;ARAUJO, MARCELO DEL FIORE DE;BASTREGHI, JEFFERSON;SCOULLER, ROSS SINCLAIR 发明人 BORRACINI, EVANDRO JOSE PITARO;ARAUJO, MARCELO DEL FIORE DE;BASTREGHI, JEFFERSON;SCOULLER, ROSS SINCLAIR
分类号 G06F13/10;G06F13/16;G06F13/38 主分类号 G06F13/10
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