| 摘要 |
<p>A data processing apparatus maps symbols received from a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed (OFDM) symbols into an output symbol stream. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift: register of R' i [10] = R' i - 1 [0] Š• R' i - 1 [2], and the permutation code forms, with an additional bit, a twelve bit address. The data processing apparatus is operable to de-interleave the first and second sets of data symbols into the output data stream in accordance with an odd interleaving process, thereby providing an improvement in interleaving the data symbols for a 4K operating mode of an OFDM modulated system such as a Digital Video Broadcasting (DVB) standard such as DVB-Terrestrial2 (DVB-T2). This is because there is a reduced likelihood that successive data bits which are close in order in an input data stream are mapped onto the same sub-carrier of an OFDM symbol.</p> |
