发明名称 Multiplexed data stream timeslot map
摘要 A network component comprising a processor configured to implement a method comprising promoting the communication of a frame within a synchronization window, wherein the frame comprises a plurality of data types assigned to a plurality of timeslots, and a timeslot map indicating the data type assigned to each timeslot. Also disclosed is a method comprising receiving a data stream comprising a data structure comprising a plurality of timeslots, each timeslot carrying one of a plurality of data types, receiving a timeslot map indicating the data types assigned to each of the timeslots, and processing each timeslot in accordance with the timeslot map.
申请公布号 US7961751(B2) 申请公布日期 2011.06.14
申请号 US20070735602 申请日期 2007.04.16
申请人 FUTUREWEI TECHNOLOGIES, INC. 发明人 FOURCAND SERGE FRANCOIS
分类号 H04B7/212;H04J3/00 主分类号 H04B7/212
代理机构 代理人
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