发明名称 |
Electronic design for integrated circuits based on process related variations |
摘要 |
An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.
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申请公布号 |
US7962867(B2) |
申请公布日期 |
2011.06.14 |
申请号 |
US20080021298 |
申请日期 |
2008.01.28 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
WHITE DAVID;SMITH TABER H. |
分类号 |
G06F17/50;G01Q30/02;G01Q60/00;G01Q80/00;G01Q90/00;G06F9/45;G06F19/00;H01L21/3105;H01L21/321 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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