| 摘要 |
The present invention is aimed to efficiently realize a reduction in size of and dead space in a semiconductor integrated circuit while securing freedom of placement and wiring of internal components of placement objects and suppressing an increase of constraints of CAD system. A floorplanning apparatus has a temporary placement section temporarily arranging a plurality of placement object blocks onto a mounting region so that at least two placement object blocks among the plurality of placement object blocks overlap each other to form an overlap region, and an optimization section changing arrangement of the internal components in at least one placement object block among the placement object blocks forming the overlap region while using the overlap region to optimize at least one placement object block.
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