发明名称 |
Concurrently modeling delays between points in static timing analysis operation |
摘要 |
An apparatus, program product and method perform static timing analysis on an integrated circuit design by concurrently modeling a plurality of timing delays associated with a connection between points in the design. The delays are conveyed in multiple clock signals of a single timing run of a static timing analysis operation. Multiple paths comprising logical user defined delay segments are assigned different delays. Only one signal may be permitted to propagate along each path.
|
申请公布号 |
US7962871(B2) |
申请公布日期 |
2011.06.14 |
申请号 |
US20080126037 |
申请日期 |
2008.05.23 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DARSOW CRAIG M.;HELVEY TIMOTHY D. |
分类号 |
G06F17/50;G06F9/455 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|