发明名称 Phase lock loop control system and method with non-consecutive feedback divide values
摘要 A phase-locked loop control system and method are described. Present invention phase-locked loop control systems and methods facilitate control of phase-lock loop operations. In one embodiment, phase-lock loop control systems and methods are utilized in the implementation of a modulated frequency synthesizer for facilitating efficient frequency spreading over a designated spectrum. It is appreciated that present invention embodiments can have a variety of implementations and can be compatible with vector accumulation. For example, a phase-locked loop control system or method can facilitate generation of a variety of modulation patterns, including but not necessarily limited to linear or non-linear modulation, standard or non-standard modulation, etc.
申请公布号 US7961059(B1) 申请公布日期 2011.06.14
申请号 US20060590362 申请日期 2006.10.30
申请人 CYPRESS SEMICONDUCTOR CORPORATION 发明人 LI SHULIANG
分类号 H03K21/00 主分类号 H03K21/00
代理机构 代理人
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