DIGITAL PHASE LOCKED LOOP WITH IMPROVED LOOP DELAY FEATURE
摘要
PURPOSE: A digital phase-locked loop improving a loop delay is provided to reduce a delay on a closed loop by using multi page signals with difference phases. CONSTITUTION: A reference phase accumulating part(100) outputs a standard sampling phase value by sampling an accumulated value of a reference clock phase. A phase detector(200) detects a phase difference signal corresponding to the difference between a reference sampling phase value and the DCO sampling phase value. A digital loop filter(300) averages the phase difference signal by filtering the phase difference signal. A digital control oscillator(500) generates an oscillation signal based on an averaged phase difference signal. A DCO phase accumulator(600) generates a plurality of clock signals whose phases are delayed. A plurality of D-FFs are operated according to a plurality of clock signals.
申请公布号
KR20110063006(A)
申请公布日期
2011.06.10
申请号
KR20090119924
申请日期
2009.12.04
申请人
SAMSUNG ELECTRO-MECHANICS CO., LTD.;KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY