发明名称 |
Read and volatile NV standby disturb |
摘要 |
A method of operating a nonvolatile memory circuit having a plurality of transistors arranged in series between a voltage/current source node and recall sink node includes asserting a gate bias on an isolation transistor between the source node and a charge storage transistor during nonvolatile STANDBY.
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申请公布号 |
US7957192(B2) |
申请公布日期 |
2011.06.07 |
申请号 |
US20070006225 |
申请日期 |
2007.12.31 |
申请人 |
CYPRESS SEMICONDUCTOR CORPORATION |
发明人 |
SCADE ANDREAS;GUENTHER STEFAN;HWANG JEONG-MO |
分类号 |
G11C11/34 |
主分类号 |
G11C11/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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