| 摘要 |
<p>The present invention discloses a method for generating a low-jitter clock, which comprises the following steps: interpolating time delay in each low-speed clock period to finely adjust a high-speed clock; and then performing frequency division operation on the adjusted high-speed clock to obtain a required low-speed clock. The invention also discloses a device for generating the low-jitter clock. By using the method and the device, the jitter of the low-speed clock can be reduced. The implementation method is simple and convenient and the device cost is saved.</p> |
