| 摘要 |
<p>A bus monitor circuit that outputs bus monitor output for a bus that serves to transmit data between a master unit and a slave unit comprises an access information/write data FIFO queue and a read data FIFO queue. When the property of the access information that is stored at the head of the access information/write data FIFO queue is write access, the bus monitor outputs the bus monitor access information as is, together with the corresponding write data that is transferred in the same clock cycle therewith. When the property of the access information that is stored at the head of the access information/write data FIFO queue is read access, the bus monitor circuit waits for the corresponding read data to be stored in the read data FIFO queue, and outputs the bus monitor access information and the read data as a set in the same clock cycle. The bus monitor thus ensures the order in which bus access occurs and outputs the bus monitor access information and the data information in pairs even under bus interface protocols wherein pipeline transfers are possible.</p> |
