| 摘要 |
<p>Disclosed is a processor, comprising a loop counter that is reset to zero when a loop instruction is called that executes a process within a loop from the loop start address to the loop end address, a data memory whereupon data that is employed in the process within the loop is transferred from an external source, a computation unit that employs the data that is transferred to the data memory to execute the process within the loop, a data counter that increments the loop counter by one every time a given quantity of data is transferred from the external source to the data memory, and a loop control unit that decrements the loop counter by one and causes the computation unit to execute the process within the loop when the loop count value of the loop counter is not zero.</p> |
