发明名称 |
DELAY-LOCKED LOOP CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME |
摘要 |
A delay-locked loop (DDL) circuit and a semiconductor device including the same are provided. The DDL circuit includes: a control voltage generator for generating a control voltage corresponding to a delay difference between an input clock and a plurality of comparison clocks by comparing the input clock with the plurality of comparison clocks that are sequentially generated and have different delays; a pulse width adjuster for adjusting a pulse width of the input clock according to a delay difference between the input clock and an arbitrary comparison clock of the comparison clocks and for generating a pulse-width-adjusted input clock as an adjusted input clock; and a delay unit for delaying the adjusted input clock in response to the control voltage and for outputting the delayed adjusted input clock as the comparison clocks and output clocks.
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申请公布号 |
US2011128056(A1) |
申请公布日期 |
2011.06.02 |
申请号 |
US20100950380 |
申请日期 |
2010.11.19 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
AN CHANG-HO |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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