| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a layout device for a semiconductor integrated circuit and a clock gating method, to reduce power consumption by a cell during switching. <P>SOLUTION: The layout device 51 includes an enable signal generation part 55, and a clock gating circuit addition part 56. The enable signal generation part 55 generates a second control signal input to a second clock gating circuit, based on a first control signal input to a first clock gating circuit positioned in a stage subsequent to a first branch point, and a position of a synchronizing circuit positioned in a stage subsequent to the first branch point. The clock gating circuit addition part 56 arranges the second clock gating circuit, based on the second control signal and the number of circuit elements positioned in a stage subsequent to the second clock gating circuit. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
