| 摘要 |
PROBLEM TO BE SOLVED: To provide a failure detection circuit capable of efficiently performing a test of a RAM macro output circuit. SOLUTION: The failure detection circuit is equipped with: a memory BIST 100; a plurality of RAM macro input selection circuits 110, 111 for selecting a macro test data signal S100 outputted from the memory BIST; RAM macros 120, 121 for inputting the selected macro test data signals S100; a BIST input selection circuit 200 for selecting output signals of the RAM macros 120, 121; RAM macro output selection circuits 130, 131 for selecting the output signals from the RAM macros 120, 121; flip-flops 140, 141 for holding the selected output signal; a parity generation circuit 400 for generating a parity signal from the macro test data signal S100; and parity check circuits 150, 151 for performing the parity check of the parity signal and the output signal held by the flip-flops. COPYRIGHT: (C)2011,JPO&INPIT |
