| 摘要 |
The method involves carrying out validity check of memory circuits (20A-20H) within a memory circuit stack (20), and carrying out a phase configuration on each memory circuit. The phase configuration is carried out by writing information relative to an identifier attributed to each memory circuit and information relative to the validity check result, within a configuration device of each memory circuit within the stack. The memory circuits are issued from two different wafers, where each wafer includes two memory circuits. Independent claims are also included for the following: (1) a method for addressing a memory circuit within a memory circuit stack (2) a memory circuit stack comprising two memory circuits. |
