| 摘要 |
PROBLEM TO BE SOLVED: To reduce a malfunction of a semiconductor integrated circuit caused by a production variation in via resistance. SOLUTION: An automatic wiring tool is used for detailed wiring of a semiconductor integrated circuit (S1). Then, for the semiconductor integrated circuit on which the detailed wiring is finished, static timing analysis is done on a signal path between cells (S2). Next, through the static timing analysis, a timing margin for timing constraint is obtained (S3) and a signal path is extracted that is less than a reference value at which the timing margin is established in advance. Then, the automatic wiring tool is used to preferentially insert a redundancy via into a network of signal paths where the timing margin is less than the reference value (S4, S5) and after a single via has been replaced by the redundance via based on the timing margin (S6), the timing analysis is performed again to determine whether a timing violation to the signal path exists. COPYRIGHT: (C)2011,JPO&INPIT
|
