| 摘要 |
PURPOSE: A device and method of controlling an PRF variableness are provided to variably control timing of a gate signal when changing a frequency of an PRF by using a common clock which is synchronized at a system. CONSTITUTION: An operation processor(210) selects an operation waveform mode for changeably controlling an PRF(Pulse Repletion Frequency) and designates a pulse width and cycle corresponding to the operation waveform mode. An FPGA(Field Programmable Gate Array)(220) generates the operation waveform mode, an PRF and a trigger signal. The FPGA changes a trigger time point of an enable signal of the PRF and counts a signal value of a gate which the changed PRF will be allocated. A device uses the signal value to control a timing of a signal of the gate.
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