发明名称 Scheduling in a multicore architecture
摘要 This invention relates to scheduling threads in a multicore processor. Executable transactions may scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.
申请公布号 EP2328077(A1) 申请公布日期 2011.06.01
申请号 EP20100192098 申请日期 2006.09.27
申请人 COWARE, INC.;FUJITSU MICROELECTRONICS LIMITED 发明人 LIPPETT, MARK DAVID
分类号 G06F9/40;G06F1/32 主分类号 G06F9/40
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