发明名称 |
Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor |
摘要 |
Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.
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申请公布号 |
US7951657(B2) |
申请公布日期 |
2011.05.31 |
申请号 |
US20090470001 |
申请日期 |
2009.05.21 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHENG KANGGUO;FALTERMEIER JOHNATHAN E.;FURUKAWA TOSHIHARU;HUA XUEFENG |
分类号 |
H01L21/84 |
主分类号 |
H01L21/84 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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