发明名称 |
Method and apparatus for determining write leveling delay for memory interfaces |
摘要 |
An invention is provided for determining write leveling delay for a plurality of memory devices having command signals lines connected in series to each memory device is disclosed. The invention includes determining a device delay value for each memory device. Each device delay value indicates a period of time to delay a DQS signal when accessing a related memory device. Once these delay values are determined, the delay values are examined sequentially and a prior device delay value is set to a lower value, for example zero, when a subsequent device delay value of a memory device connected subsequently along the command signal lines is greater than the prior device delay value.
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申请公布号 |
US7952945(B2) |
申请公布日期 |
2011.05.31 |
申请号 |
US20090414044 |
申请日期 |
2009.03.30 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
ESPINOZA ANNE;MACLAREN JOHN |
分类号 |
G11C7/00;G11C8/18 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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